The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for forming a transistor with a bulb-type recessed channel in a semiconductor device.
As dynamic random access memory (DRAM) devices become highly integrated, memory array transistor devices with a design rule of 100 nm or less are in demand. However, the array transistor of 100 nm or less has a very low threshold voltage characteristic due to a short channel effect. Thus, retention time decreases.
A transistor including a recessed channel has been developed in order to solve the above described limitations. The transistor including a recessed channel has a very long retention time characteristic, since it has a very long channel length unlike a typical planar type transistor.
Recently, a method to extend a length of the recessed channel has been proposed to obtain better data retention time and current characteristics than those of the recessed channel. To extend the length of the recessed channel, a bottom portion of a trench for forming the recessed channel is additionally etched to obtain a ball shape. Thus, a bulb-type recessed channel is formed. A transistor including the bulb-type recessed channel is referred to as a bulb-type recessed channel array transistor (BRCAT).
FIG. 1 illustrates a method for fabricating a transistor with a conventional bulb-type recessed channel. A bulb-type recessed region including a trench pattern 12A and a ball pattern 12B is formed over a substrate 11. A gate insulating layer 13 is formed over the surface profile of the bulb-type recessed region and the substrate 11. A gate conductive layer 14 for use as a gate electrode is formed over the gate insulating layer 13 and fills in the bulb-type recessed region. The gate electrode 14 may include polysilicon.
However, when forming the conventional bulb-type recessed channel, the ball pattern 12B has a wider width than the trench pattern 12A in the bulb-type recessed region. Thus, the gate conductive layer 14 may not completely fill the ball pattern 12B during formation. Consequently, a void V may be formed in the middle of the ball pattern 12B. As the gate conductive layer 14 is recrystallized by a subsequent high temperature thermal process, the void may move toward the gate insulating layer 13. The void may result in a portion where the gate insulating layer 13 and the gate conductive layer 14 are not directly in contact with each other.
FIG. 2A illustrates a cross-sectional view of a movement of the void after the subsequent high temperature thermal process is performed and FIG. 2B illustrates a micrographic view of the movement of the void after the subsequent high temperature thermal process is performed. The subsequent high temperature thermal process is performed at a temperature ranging from approximately 650° C. to approximately 1,050° C. The gate conductive layer 14 includes polysilicon. The void moves from the middle of the ball pattern 12B to an interface of the gate insulating layer 13 during the subsequent high temperature thermal process. Thus, the void may contact the gate insulating layer 13.
The void moves because vacancies melted in equilibrium in the gate conductive layer 14 cause growing and moving of the void during a subsequent thermal process. The vacancy is a lattice defect in a crystal lattice where an atom is missing. Specifically, the void is a portion where the gate conductive layer 14 does not contact the interface of the gate insulating layer 13. Thus, the portion, i.e. the void, may result in a decrease of channel capacitance, causing a drain current to decrease. Moreover, a threshold voltage may be difficult to control due to the void.